1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently determining whether a requested memory location is in a large row-based memory of a computing system.
2. Description of the Relevant Art
As both semiconductor manufacturing processes advance and on-die geometric dimensions reduce, semiconductor chips provide more functionality and performance. However, design issues still arise with modern techniques in processing and integrated circuit design that may limit potential benefits. One issue is interconnect delays continue to increase per unit length in successive generations of two-dimensional planar layout chips. High electrical impedance between individual chips increases latency. In addition, signals that traverse off-chip to another chip increase power consumption for these signals due to the increased parasitic capacitance on these longer signal routes.
Another design issue is most software applications that access a lot of data are typically memory bound. A memory access latency for an off-chip dynamic random access memory (DRAM) may be hundreds to over a thousand clock cycles. An increased number of cores in a processor design have accentuated the memory bandwidth problem. Recently, progress has been made in three-dimensional integrated circuits (3D ICs) that include two or more layers of active electronic components integrated both vertically and horizontally into a single circuit. The 3D packaging, known as System in Package (SiP) or Chip Stack multi-chip module (MCM), stacks separate chips in a single package. All components on the layers communicate using on-chip signaling, whether vertically or horizontally. This signaling provides reduced interconnect signal delay over known two-dimensional planar layout circuits.
The manufacturing trends in the above description may lead to gigabytes of integrated memory within a package. Additional on-chip storage may be used as a row-based memory, such as a last-level cache (LLC) before accessing off-chip memory. A reduced miss rate achieved by the additional memory helps hide the latency gap between a processor and its off-chip memory. In addition, power consumption may be reduced and utilization of buses may become more efficient.
Although a cache hit within a large on-chip LLC may reduce the latency to retrieve requested data, a cache miss may increase the overall latency. To save bandwidth and power consumption, the memory request may not be sent to the off-chip memory until a hit/miss result for the large on-chip LLC is known. A mechanism for determining whether a memory request may find a requested memory location within the large on-chip LLC may allow the memory request to be sent earlier to the off-chip memory. Thus, power consumption may be reduced as the large on-chip LLC is not accessed and the over all memory latency may also be reduced.
In view of the above, efficient methods and systems for determining whether a requested memory location is in a large row-based memory of a computing system are desired.